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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [verilog/] [top.syn] - Rev 133

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133 Added Desing databases and foundation for elaborations tools jt_eaton 3498d 04h /socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.syn
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3530d 01h /socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.syn

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