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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Rev 135

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Rev Log message Author Age Path
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.
jt_eaton 3455d 01h /socgen/trunk/common/opencores.org/Testbench/bfms/vga_model/rtl/verilog/top.rtl
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3529d 23h /socgen/trunk/common/opencores.org/Testbench/bfms/vga_model/rtl/verilog/top.rtl

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