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[/] [socgen/] [trunk/] [tools/] [simulation/] [build_coverage] - Rev 133

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Rev Log message Author Age Path
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3514d 19h /socgen/trunk/tools/simulation/build_coverage
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley
jt_eaton 3618d 13h /socgen/trunk/tools/simulation/build_coverage
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools
jt_eaton 4073d 19h /socgen/trunk/tools/simulation/build_coverage
127 final cleanup before DAC jt_eaton 4188d 15h /socgen/trunk/tools/simulation/build_coverage
126 added mor1kx
cleanup
jt_eaton 4241d 20h /socgen/trunk/tools/simulation/build_coverage
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control
jt_eaton 4286d 14h /socgen/trunk/tools/simulation/build_coverage
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem
jt_eaton 4339d 17h /socgen/trunk/tools/simulation/build_coverage
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4435d 13h /socgen/trunk/tools/simulation/build_coverage

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