URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] [build_generate] - Rev 135

Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2945d 03h	/socgen/trunk/tools/sys/build_generate
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3498d 06h	/socgen/trunk/tools/sys/build_generate
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3530d 03h	/socgen/trunk/tools/sys/build_generate
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3633d 20h	/socgen/trunk/tools/sys/build_generate
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4089d 02h	/socgen/trunk/tools/sys/build_generate
127	final cleanup before DAC	jt_eaton	4203d 23h	/socgen/trunk/tools/sys/build_generate
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4450d 20h	/socgen/trunk/tools/sys/build_generate
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4486d 05h	/socgen/trunk/tools/sys/build_generate
117	added yellow pages tools	jt_eaton	4514d 00h	/socgen/trunk/tools/sys/build_generate