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[/] [socgen/] [trunk/] [tools/] [sys/] [build_generate] - Rev 127

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Rev Log message Author Age Path
127 final cleanup before DAC jt_eaton 4207d 20h /socgen/trunk/tools/sys/build_generate
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4454d 17h /socgen/trunk/tools/sys/build_generate
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4490d 03h /socgen/trunk/tools/sys/build_generate
117 added yellow pages tools jt_eaton 4517d 21h /socgen/trunk/tools/sys/build_generate

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