URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] [build_generate] - Rev 134

Rev	Log message	Author	Age	Path
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3501d 21h	/socgen/trunk/tools/sys/build_generate
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3533d 18h	/socgen/trunk/tools/sys/build_generate
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3637d 11h	/socgen/trunk/tools/sys/build_generate
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4092d 18h	/socgen/trunk/tools/sys/build_generate
127	final cleanup before DAC	jt_eaton	4207d 14h	/socgen/trunk/tools/sys/build_generate
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4454d 11h	/socgen/trunk/tools/sys/build_generate
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4489d 21h	/socgen/trunk/tools/sys/build_generate
117	added yellow pages tools	jt_eaton	4517d 16h	/socgen/trunk/tools/sys/build_generate