OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] [soc_link_child] - Rev 130

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley		 jt_eaton 3633d 20h /socgen/trunk/tools/sys/soc_link_child
127 final cleanup before DAC jt_eaton 4203d 23h /socgen/trunk/tools/sys/soc_link_child
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 4301d 21h /socgen/trunk/tools/sys/soc_link_child
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 4355d 00h /socgen/trunk/tools/sys/soc_link_child
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code		 jt_eaton 4398d 02h /socgen/trunk/tools/sys/soc_link_child
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench		 jt_eaton 4416d 02h /socgen/trunk/tools/sys/soc_link_child
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4450d 20h /socgen/trunk/tools/sys/soc_link_child
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4486d 05h /socgen/trunk/tools/sys/soc_link_child
117 added yellow pages tools jt_eaton 4514d 00h /socgen/trunk/tools/sys/soc_link_child
115 split or1200_cpu up into all ip-xact components
removed dead files		 jt_eaton 4593d 02h /socgen/trunk/tools/sys/soc_link_child
107 added designCfg files to all modules jt_eaton 4638d 07h /socgen/trunk/tools/sys/soc_link_child
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4731d 19h /socgen/trunk/tools/sys/soc_link_child
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4786d 19h /socgen/trunk/tools/sys/soc_link_child
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4932d 20h /socgen/trunk/tools/sys/soc_link_child

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.