URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] [workspace] - Rev 121

Rev	Log message	Author	Age	Path
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4454d 12h	/socgen/trunk/tools/sys/workspace
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4489d 21h	/socgen/trunk/tools/sys/workspace
117	added yellow pages tools	jt_eaton	4517d 16h	/socgen/trunk/tools/sys/workspace
110	split out more ip-xact components added sw sources	jt_eaton	4637d 14h	/socgen/trunk/tools/sys/workspace
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4747d 18h	/socgen/trunk/tools/sys/workspace
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4790d 11h	/socgen/trunk/tools/sys/workspace
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4826d 16h	/socgen/trunk/tools/sys/workspace
96	hierConnections now create ports	jt_eaton	4900d 12h	/socgen/trunk/tools/sys/workspace
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4909d 10h	/socgen/trunk/tools/sys/workspace
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4936d 11h	/socgen/trunk/tools/sys/workspace