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[/] [socgen/] [trunk/] [tools/] [sys/] [workspace] - Rev 127

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Rev	Log message	Author	Age	Path
127	final cleanup before DAC	jt_eaton	4204d 03h	/socgen/trunk/tools/sys/workspace
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4355d 05h	/socgen/trunk/tools/sys/workspace
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4451d 01h	/socgen/trunk/tools/sys/workspace
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4486d 10h	/socgen/trunk/tools/sys/workspace
117	added yellow pages tools	jt_eaton	4514d 05h	/socgen/trunk/tools/sys/workspace
110	split out more ip-xact components added sw sources	jt_eaton	4634d 03h	/socgen/trunk/tools/sys/workspace
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4744d 07h	/socgen/trunk/tools/sys/workspace
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4787d 00h	/socgen/trunk/tools/sys/workspace
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4823d 05h	/socgen/trunk/tools/sys/workspace
96	hierConnections now create ports	jt_eaton	4897d 01h	/socgen/trunk/tools/sys/workspace
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4905d 23h	/socgen/trunk/tools/sys/workspace
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4933d 00h	/socgen/trunk/tools/sys/workspace

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