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[/] [socgen/] [trunk/] [tools/] [sys/] [workspace] - Rev 128

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Rev Log message Author Age Path
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools		 jt_eaton 4089d 01h /socgen/trunk/tools/sys/workspace
127 final cleanup before DAC jt_eaton 4203d 21h /socgen/trunk/tools/sys/workspace
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 4354d 23h /socgen/trunk/tools/sys/workspace
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4450d 19h /socgen/trunk/tools/sys/workspace
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4486d 04h /socgen/trunk/tools/sys/workspace
117 added yellow pages tools jt_eaton 4513d 23h /socgen/trunk/tools/sys/workspace
110 split out more ip-xact components
added sw sources		 jt_eaton 4633d 22h /socgen/trunk/tools/sys/workspace
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4744d 01h /socgen/trunk/tools/sys/workspace
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4786d 18h /socgen/trunk/tools/sys/workspace
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4822d 23h /socgen/trunk/tools/sys/workspace
96 hierConnections now create ports jt_eaton 4896d 19h /socgen/trunk/tools/sys/workspace
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc		 jt_eaton 4905d 17h /socgen/trunk/tools/sys/workspace
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4932d 18h /socgen/trunk/tools/sys/workspace

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