URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilog] - Rev 127

Rev	Log message	Author	Age	Path
127	final cleanup before DAC	jt_eaton	4207d 18h	/socgen/trunk/tools/verilog/gen_verilog
126	added mor1kx cleanup	jt_eaton	4260d 23h	/socgen/trunk/tools/verilog/gen_verilog
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4305d 17h	/socgen/trunk/tools/verilog/gen_verilog
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4358d 20h	/socgen/trunk/tools/verilog/gen_verilog
123	added support for ubuntu 12.10	jt_eaton	4373d 12h	/socgen/trunk/tools/verilog/gen_verilog
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4381d 15h	/socgen/trunk/tools/verilog/gen_verilog
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4401d 21h	/socgen/trunk/tools/verilog/gen_verilog
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4419d 21h	/socgen/trunk/tools/verilog/gen_verilog
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4454d 15h	/socgen/trunk/tools/verilog/gen_verilog