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[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Rev 121

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Rev Log message Author Age Path
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4419d 15h /socgen/trunk/tools/verilog/gen_verilogLib
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4454d 10h /socgen/trunk/tools/verilog/gen_verilogLib

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