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[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Rev 127

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Rev Log message Author Age Path
127 final cleanup before DAC jt_eaton 4204d 01h /socgen/trunk/tools/verilog/gen_verilogLib
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4416d 05h /socgen/trunk/tools/verilog/gen_verilogLib
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4450d 23h /socgen/trunk/tools/verilog/gen_verilogLib

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