URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Rev 134

Rev	Log message	Author	Age	Path
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3455d 04h	/socgen/trunk/tools/verilog/gen_verilogLib
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3530d 02h	/socgen/trunk/tools/verilog/gen_verilogLib
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3633d 19h	/socgen/trunk/tools/verilog/gen_verilogLib
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4089d 01h	/socgen/trunk/tools/verilog/gen_verilogLib
127	final cleanup before DAC	jt_eaton	4203d 21h	/socgen/trunk/tools/verilog/gen_verilogLib
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4416d 01h	/socgen/trunk/tools/verilog/gen_verilogLib
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4450d 19h	/socgen/trunk/tools/verilog/gen_verilogLib