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[/] [socgen/] [trunk/] [tools/] [yp/] [lib.pm] - Rev 134

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Rev Log message Author Age Path
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.		 jt_eaton 3458d 21h /socgen/trunk/tools/yp/lib.pm
133 Added Desing databases and foundation for elaborations tools jt_eaton 3501d 22h /socgen/trunk/tools/yp/lib.pm
131 Added elaboration databases and tools
Added bus map creation tools		 jt_eaton 3533d 19h /socgen/trunk/tools/yp/lib.pm
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley		 jt_eaton 3637d 12h /socgen/trunk/tools/yp/lib.pm
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools		 jt_eaton 4092d 18h /socgen/trunk/tools/yp/lib.pm
127 final cleanup before DAC jt_eaton 4207d 14h /socgen/trunk/tools/yp/lib.pm
126 added mor1kx
cleanup		 jt_eaton 4260d 19h /socgen/trunk/tools/yp/lib.pm
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 4305d 13h /socgen/trunk/tools/yp/lib.pm
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 4358d 16h /socgen/trunk/tools/yp/lib.pm
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components		 jt_eaton 4381d 12h /socgen/trunk/tools/yp/lib.pm
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench		 jt_eaton 4419d 18h /socgen/trunk/tools/yp/lib.pm
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4489d 21h /socgen/trunk/tools/yp/lib.pm
117 added yellow pages tools jt_eaton 4517d 16h /socgen/trunk/tools/yp/lib.pm

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