URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [tags/] [rel_7/] [rtl/] [verilog/] [spi_top.v] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5660d 00h	/spi/tags/rel_7/rtl/verilog/spi_top.v
24	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7731d 18h	/spi/tags/rel_7/rtl/verilog/spi_top.v
21	Byte selects changed.	simons	7731d 18h	/spi/tags/rel_7/rtl/verilog/spi_top.v
15	Defines set in order.	simons	7735d 23h	/spi/tags/rel_7/rtl/verilog/spi_top.v
13	8-bit WB access enabled.	simons	7736d 16h	/spi/tags/rel_7/rtl/verilog/spi_top.v
10	Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.	simons	7774d 22h	/spi/tags/rel_7/rtl/verilog/spi_top.v
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7815d 16h	/spi/tags/rel_7/rtl/verilog/spi_top.v
8	Automatic slave select signal generation added.	simons	7835d 17h	/spi/tags/rel_7/rtl/verilog/spi_top.v
7	Support for 64 bit caharacter len added.	simons	7924d 06h	/spi/tags/rel_7/rtl/verilog/spi_top.v
2	Initial import	simons	8122d 18h	/spi/tags/rel_7/rtl/verilog/spi_top.v