| Rev |
Log message |
Author |
Age |
Path |
| 23 |
Clarified copyright and licensing
Added trunk/license directory
Added LGPL 3.0 license text "lgpl.txt"
Fixed inline url for the GNU link of the LGPL license
Updated readme files and rtl files |
jdoin |
4862d 01h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 22 |
spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. |
jdoin |
4863d 12h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 16 |
Master: v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
Slave: v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. |
jdoin |
4887d 11h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 14 |
Updated specifications manual, deleted old documentation stuff, changed minor text errors in the code. |
jdoin |
4889d 15h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 13 |
spi_slave.vhd: v2.02.0120
spi_master.vhd: v1.15.0135
Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers. |
jdoin |
4890d 10h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 12 |
SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks. |
jdoin |
4894d 10h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 11 |
v1.12.0105: Modified SCK output circuit in spi_master.vhd.
In CPHA='0', top speed is +50MHz, in CPHA='1', top speed is 25MHz. |
jdoin |
4905d 09h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 10 |
v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise. |
jdoin |
4906d 10h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 7 |
Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. |
jdoin |
4910d 13h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 6 |
v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
4912d 10h |
/spi_master_slave/trunk/syn/spi_master.vhd |
| 5 |
Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
4912d 10h |
/spi_master_slave/trunk/syn/spi_master.vhd |
