URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_slave.vhd] - Rev 17

Rev	Log message	Author	Age	Path
16	Master: v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs. Slave: v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.	jdoin	4888d 00h	/spi_master_slave/trunk/syn/spi_slave.vhd
13	spi_slave.vhd: v2.02.0120 spi_master.vhd: v1.15.0135 Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers.	jdoin	4890d 23h	/spi_master_slave/trunk/syn/spi_slave.vhd
12	SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs: -- - redesigned core clocking to address all CPOL and CPHA configurations. -- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite -- clock phases from SHIFT_EDGE. -- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions -- for each state, to avoid reported inference problems in some synthesis engines. -- Streamlined port names and indentation blocks.	jdoin	4894d 23h	/spi_master_slave/trunk/syn/spi_slave.vhd
10	v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register). Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.	jdoin	4907d 00h	/spi_master_slave/trunk/syn/spi_slave.vhd