URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_test_ct.wcfg] - Rev 25

Rev	Log message	Author	Age	Path
24	- fixed range of the switch debouncer for the verification circuit - reorganized rtl folder in mainstream trunk	jdoin	4842d 16h	/spi_master_slave/trunk/syn/spi_test_ct.wcfg
20	- removed folder trunk/bench. - added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.	jdoin	4882d 09h	/spi_master_slave/trunk/syn/spi_test_ct.wcfg
13	spi_slave.vhd: v2.02.0120 spi_master.vhd: v1.15.0135 Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers.	jdoin	4891d 06h	/spi_master_slave/trunk/syn/spi_test_ct.wcfg