URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [usage_statistics_webtalk.html] - Rev 22

Rev	Log message	Author	Age	Path
22	spi_slave.vhd: v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'. FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.	jdoin	4820d 18h	/spi_master_slave/trunk/syn/usage_statistics_webtalk.html
20	- removed folder trunk/bench. - added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.	jdoin	4838d 19h	/spi_master_slave/trunk/syn/usage_statistics_webtalk.html
11	v1.12.0105: Modified SCK output circuit in spi_master.vhd. In CPHA='0', top speed is +50MHz, in CPHA='1', top speed is 25MHz.	jdoin	4862d 15h	/spi_master_slave/trunk/syn/usage_statistics_webtalk.html