URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [bench_fifo_s.v] - Rev 31

Rev	Log message	Author	Age	Path
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5408d 17h	/srdydrdy_lib/trunk/env/verilog/bench_fifo_s.v
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5422d 17h	/srdydrdy_lib/trunk/env/verilog/bench_fifo_s.v