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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [common/] [sd_seq_check.v] - Rev 31

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22 Created separate module-level environments for fifo_b
and scoreboard. Added some documentation on the
example bridge, including a PDF preso giving a basic
introduction to ethernet.
ghutchis 5407d 21h /srdydrdy_lib/trunk/env/verilog/common/sd_seq_check.v
3 Added small/synchronizer FIFO, along with minimal testbench ghutchis 5426d 11h /sd_seq_check.v

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