URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [common/] [sd_seq_gen.v] - Rev 31

Rev	Log message	Author	Age	Path
22	Created separate module-level environments for fifo_b and scoreboard. Added some documentation on the example bridge, including a PDF preso giving a basic introduction to ethernet.	ghutchis	5407d 21h	/srdydrdy_lib/trunk/env/verilog/common/sd_seq_gen.v
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5412d 12h	/sd_seq_gen.v
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5426d 12h	/sd_seq_gen.v