URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [fifo_b/] [bench_fifo_b.vf] - Rev 30

Rev	Log message	Author	Age	Path
22	Created separate module-level environments for fifo_b and scoreboard. Added some documentation on the example bridge, including a PDF preso giving a basic introduction to ethernet.	ghutchis	5420d 22h	/srdydrdy_lib/trunk/env/verilog/fifo_b/bench_fifo_b.vf
6	Modified "B" output buffer for full-rate operation	ghutchis	5437d 03h	/bench_fifo_b.vf