URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_s.v] - Rev 17

Rev	Log message	Author	Age	Path
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5412d 07h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_s.v
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5417d 16h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_s.v
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5426d 07h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_s.v