OpenCores

URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_tail_b.v] - Rev 22

Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
22	Created separate module-level environments for fifo_b and scoreboard. Added some documentation on the example bridge, including a PDF preso giving a basic introduction to ethernet.	ghutchis	5424d 20h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
19	Fixed several minor bugs in scoreboard, adjusted usage width in sd_fifo_b, and updated component documentation.	ghutchis	5426d 12h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
16	Changed fifo head/tail to have separate usage counters for producer and consumer side. Fixed bug in port_ring_tap where it jumped to non-existent state. Changed default dump mode for icarus to lxt.	ghutchis	5427d 13h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5429d 11h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
13	Fixed FIFO Full condition for large fifo, added separate tests to example bridge	ghutchis	5432d 22h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5434d 20h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
6	Modified "B" output buffer for full-rate operation	ghutchis	5441d 01h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
2	Initial commit of directory structure and basic components	ghutchis	5447d 20h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.