URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_1_beta/] [bench/] [vhdl/] [tb.vhd] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5610d 04h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
251	This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'.		6580d 13h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
83	connect if_timing to P2 output of T48	arniml	7389d 17h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
80	added if_timing	arniml	7389d 22h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7400d 17h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
33	rename pX_limp to pX_low_imp	arniml	7416d 18h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
30	connect prog_n_o	arniml	7417d 17h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
19	enhance simulation result string	arniml	7419d 15h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7421d 15h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd
8	initial check-in	arniml	7421d 16h	/t48/tags/rel_0_1_beta/bench/vhdl/tb.vhd