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[/] [t48/] [tags/] [rel_0_4_beta/] [rtl/] [vhdl/] [decoder.vhd] - Rev 303

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292 New directory structure. root 5602d 19h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
254 This commit was manufactured by cvs2svn to create tag 'rel_0_4_beta'. 6573d 04h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7243d 05h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7316d 08h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
106 clean-up use of ea_i arniml 7357d 07h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
101 assert p2_read_p2_o when expander port is read arniml 7360d 14h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
92 work around bug in Quartus II 4.0 arniml 7361d 14h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
78 adjust external timing of BUS arniml 7382d 13h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
72 removed superfluous signal from sensitivity list arniml 7383d 18h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions		 arniml 7389d 10h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls		 arniml 7392d 07h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
53 make istrobe visible through testbench package arniml 7393d 08h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
45 remove unused signals arniml 7400d 07h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
38 add measures to implement XCHD arniml 7403d 15h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
27 implemented mnemonic DA arniml 7410d 08h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A		 arniml 7410d 16h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd
4 initial check-in arniml 7415d 08h /t48/tags/rel_0_4_beta/rtl/vhdl/decoder.vhd

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