URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [rtl/] [vhdl/] [clock_ctrl.vhd] - Rev 329

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5607d 19h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
255	This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'.		6578d 03h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
145	remove PROG and end of XTAL2, see comment for details	arniml	7204d 08h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7204d 09h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
77	move from std_logic_arith to numeric_std	arniml	7388d 05h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7394d 10h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
20	move code for PROG out of if-branch for xtal3_s	arniml	7415d 16h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd
4	initial check-in	arniml	7420d 07h	/t48/tags/rel_0_5_beta/rtl/vhdl/clock_ctrl.vhd