URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] [rtl/] [vhdl/] [timer.vhd] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5637d 18h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd
255	This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'.		6608d 03h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd
129	cleanup copyright notice	arniml	7340d 11h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7347d 15h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd
91	fix edge detector bug for counter	arniml	7396d 12h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd
59	increment prescaler with MSTATE4	arniml	7427d 06h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd
4	initial check-in	arniml	7450d 06h	/t48/tags/rel_0_5_beta/rtl/vhdl/timer.vhd