URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6__beta/] [rtl/] [vhdl/] [t48_core.vhd] - Rev 339

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5648d 22h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
257	This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'.		6619d 07h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	7016d 22h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7054d 11h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
86	update notice about expander port instructions	arniml	7422d 20h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
45	remove unused signals	arniml	7446d 10h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
38	add measures to implement XCHD	arniml	7449d 17h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
32	rename pX_limp to pX_low_imp	arniml	7455d 12h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
28	update wiring for DA support	arniml	7456d 10h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
24	connect control signal for Port 2 expander	arniml	7456d 18h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd
4	initial check-in	arniml	7461d 10h	/t48/tags/rel_0_6__beta/rtl/vhdl/t48_core.vhd