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[/] [t48/] [tags/] [rel_0_6_beta/] [bench/] [vhdl/] [tb.vhd] - Rev 294

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292 New directory structure. root 5601d 21h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
258 This commit was manufactured by cvs2svn to create tag 'rel_0_6_beta'. 6572d 06h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
183 fix missing assignment to outclock arniml 6881d 13h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7355d 19h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7359d 16h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
83 connect if_timing to P2 output of T48 arniml 7381d 10h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
80 added if_timing arniml 7381d 14h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator		 arniml 7392d 10h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
33 rename pX_limp to pX_low_imp arniml 7408d 11h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
30 connect prog_n_o arniml 7409d 09h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
19 enhance simulation result string arniml 7411d 08h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7413d 07h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd
8 initial check-in arniml 7413d 09h /t48/tags/rel_0_6_beta/bench/vhdl/tb.vhd

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