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[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] [vhdl/] [decoder.vhd] - Rev 295

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292 New directory structure. root 5667d 09h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
258 This commit was manufactured by cvs2svn to create tag 'rel_0_6_beta'. 6637d 18h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6940d 22h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7035d 09h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7036d 21h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
171 remove obsolete output stack_high_o arniml 7067d 21h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7263d 23h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7307d 18h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7380d 22h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
106 clean-up use of ea_i arniml 7421d 21h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
101 assert p2_read_p2_o when expander port is read arniml 7425d 04h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
92 work around bug in Quartus II 4.0 arniml 7426d 03h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
78 adjust external timing of BUS arniml 7447d 03h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
72 removed superfluous signal from sensitivity list arniml 7448d 08h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions		 arniml 7454d 00h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls		 arniml 7456d 21h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
53 make istrobe visible through testbench package arniml 7457d 22h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
45 remove unused signals arniml 7464d 21h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
38 add measures to implement XCHD arniml 7468d 05h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd
27 implemented mnemonic DA arniml 7474d 22h /t48/tags/rel_0_6_beta/rtl/vhdl/decoder.vhd

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