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[/] [t48/] [tags/] [rel_1_0/] [bench/] [vhdl/] [tb.vhd] - Rev 329

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5601d 22h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6414d 08h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
228	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom	arniml	6595d 07h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
220	new input xtal_en_i	arniml	6596d 07h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
201	split low impedance markers for P2	arniml	6826d 11h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
183	fix missing assignment to outclock	arniml	6881d 14h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
111	split 4k internal ROM into + 2k internal ROM + 2k external ROM EA of t48_core is driven by MSB of internal ROM address if upper 2k block is selected, the system switches to EA mode on the fly	arniml	7355d 21h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
103	add testbench peripherals for P1 and P2 this became necessary to observe a difference between externally applied port data and internally applied port data	arniml	7359d 17h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
83	connect if_timing to P2 output of T48	arniml	7381d 11h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
80	added if_timing	arniml	7381d 16h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7392d 11h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
33	rename pX_limp to pX_low_imp	arniml	7408d 12h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
30	connect prog_n_o	arniml	7409d 10h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
19	enhance simulation result string	arniml	7411d 09h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7413d 09h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd
8	initial check-in	arniml	7413d 10h	/t48/tags/rel_1_0/bench/vhdl/tb.vhd

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