URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [bench/] [vhdl/] [tb_t8048.vhd] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5608d 17h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6421d 03h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
240	comment added about lower 1k of external ROM	arniml	6599d 02h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
233	added external ROM	arniml	6601d 02h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
228	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom	arniml	6602d 02h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
68	connect T0 and T1 to P1	arniml	7395d 08h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7399d 06h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
19	enhance simulation result string	arniml	7418d 04h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd
8	initial check-in	arniml	7420d 05h	/t48/tags/rel_1_0/bench/vhdl/tb_t8048.vhd