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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [clock_ctrl.vhd] - Rev 294

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Rev Log message Author Age Path
292 New directory structure. root 5601d 02h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
277 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6413d 12h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
249 Fix bug report
"Deassertion of PROG too early"
PROG is deasserted at end of XTAL3 now		 arniml 6571d 11h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
219 new input xtal_en_i gates xtal_i base clock arniml 6595d 11h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6825d 15h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6969d 02h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6970d 14h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7006d 16h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
145 remove PROG and end of XTAL2, see comment for details arniml 7197d 15h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7197d 16h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
77 move from std_logic_arith to numeric_std arniml 7381d 12h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset		 arniml 7387d 17h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
20 move code for PROG out of if-branch for xtal3_s arniml 7408d 23h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd
4 initial check-in arniml 7413d 14h /t48/tags/rel_1_0/rtl/vhdl/clock_ctrl.vhd

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