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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [decoder.vhd] - Rev 292

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5614d 16h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6427d 03h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
220	new input xtal_en_i	arniml	6609d 01h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
215	suppress p2_output_pch_o when MOVX operation is accessing the external memory	arniml	6826d 05h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
214	fix sensitivity list	arniml	6833d 07h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
204	* suppress p2_output_pch_o when p2_output_exp is active * wire xtal_i to interrupt module	arniml	6839d 05h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
195	Suppress assertion of bus_read_bus_s when interrupt is pending. This should fix bug report "PROBLEM WHEN INT AND JMP"	arniml	6840d 16h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6888d 05h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6982d 16h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6984d 04h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
171	remove obsolete output stack_high_o	arniml	7015d 04h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7211d 07h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7255d 02h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7328d 05h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
106	clean-up use of ea_i	arniml	7369d 04h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
101	assert p2_read_p2_o when expander port is read	arniml	7372d 12h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
92	work around bug in Quartus II 4.0	arniml	7373d 11h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
78	adjust external timing of BUS	arniml	7394d 10h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
72	removed superfluous signal from sensitivity list	arniml	7395d 15h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7401d 07h	/t48/tags/rel_1_0/rtl/vhdl/decoder.vhd

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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [decoder.vhd] - Rev 292

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