OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [wb_master.vhd] - Rev 294

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5601d 04h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
277 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6413d 14h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6969d 04h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48
arniml 7000d 15h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
167 simplify address range:
- configuration range
- Wishbone range
arniml 7003d 03h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
166 assign default for state_s arniml 7004d 19h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
164 initial check-in arniml 7005d 18h /t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.