OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [timer.vhd] - Rev 292

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5638d 08h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
277 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6450d 18h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
273 reset counter_q arniml 6469d 03h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7006d 07h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
129 cleanup copyright notice arniml 7341d 01h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered
arniml 7348d 05h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
91 fix edge detector bug for counter arniml 7397d 02h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
59 increment prescaler with MSTATE4 arniml 7427d 20h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd
4 initial check-in arniml 7450d 20h /t48/tags/rel_1_0/rtl/vhdl/timer.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.