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[/] [t48/] [tags/] [rel_1_0/] [sim/] [rtl_sim/] [Makefile.ghdl] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5604d 00h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6416d 10h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
259	added t8243 core plus related testbenches	arniml	6574d 08h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
232	update to new memory concept	arniml	6597d 08h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
218	simplifications	arniml	6684d 16h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
154	added t8039_notri hierarchy	arniml	7161d 14h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7163d 02h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7346d 13h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
93	add support for line coverage evaluation with gcov	arniml	7362d 18h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
79	add if_timing module	arniml	7383d 17h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
77	move from std_logic_arith to numeric_std	arniml	7384d 10h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
75	remove obsolete design unit	arniml	7384d 14h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
71	add T8039 and its testbench	arniml	7390d 15h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
16	fix header	arniml	7413d 11h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
11	add description	arniml	7414d 12h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl
9	initial check-in	arniml	7415d 10h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.ghdl