URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_2/] [bench/] [vhdl/] [tb_t8048.vhd] - Rev 300

Rev	Log message	Author	Age	Path
300	maintenance release for svn updates	arniml	5523d 13h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
295	- remove unsupported CVS tags - propset for Id	arniml	5580d 16h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
292	New directory structure.	root	5603d 01h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
282	decouple bidir port T0 from P1 fixes testcase black_box/tx/t0	arniml	5918d 13h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
240	comment added about lower 1k of external ROM	arniml	6593d 10h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
233	added external ROM	arniml	6595d 11h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
228	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom	arniml	6596d 10h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
68	connect T0 and T1 to P1	arniml	7389d 16h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7393d 14h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
19	enhance simulation result string	arniml	7412d 12h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd
8	initial check-in	arniml	7414d 13h	/t48/tags/rel_1_2/bench/vhdl/tb_t8048.vhd