URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp.v] - Rev 218

Rev	Log message	Author	Age	Path
187	Fixed the module name.	creep	5679d 23h	/t6507lp/trunk/rtl/verilog/t6507lp.v
136	Some minor coding style changes.	gabrieloshiro	5696d 03h	/t6507lp/trunk/rtl/verilog/t6507lp.v
128	$write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized.	gabrieloshiro	5700d 06h	/t6507lp/trunk/rtl/verilog/t6507lp.v
118	The top level name was in uppercase. The correct is lowercase.	creep	5702d 06h	/t6507lp/trunk/rtl/verilog/t6507lp.v