URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Rev 156

Rev	Log message	Author	Age	Path
156	Some bugs were fixed. Testbench were expecting wrong values sometimes.	gabrieloshiro	5567d 02h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
150	Bug #24 from trac might be fixed. Processor register is working properly.	gabrieloshiro	5568d 01h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
149	Bug #24 from trac might be fixed. Processor register is working properly.	gabrieloshiro	5568d 02h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
148	Reset assertion was commented. It was not working properly.	gabrieloshiro	5568d 02h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
145	ASL instruction fixed. For some reason the operator "<<" is not working properly.	gabrieloshiro	5569d 01h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
143	Modified the inputs so the alu resets.	creep	5569d 02h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
140	Variable names were changed according to coding guidelines.	gabrieloshiro	5569d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
136	Some minor coding style changes.	gabrieloshiro	5570d 02h	/t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
127	Testbench created. Simulation is almost done! Everything seems to be working fine.	gabrieloshiro	5574d 06h	/t6507lp/trunk/rtl/verilog/T6507LP_ALU_TestBench.v