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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 106

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105 The RTI instruction is working fine. Coded and simulated. creep 5703d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104 The BRK instruction is working. The reset vector was tested also. creep 5703d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103 Some early modifications to support the special stack instructions. creep 5704d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102 Some early modifications to support the special stack instructions. creep 5704d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101 Absolute indirect addressing mode is coded and simulated. creep 5704d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 5704d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5707d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5707d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5708d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5708d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5709d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86 Zero page indexed mode is working fine. creep 5709d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5709d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5710d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
78 ZPG coded and simulated. creep 5710d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
77 ZPG coded. Simulation is halfway. creep 5710d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5710d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5714d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5714d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
63 Fixed several HAL warnings. Still plenty to do. creep 5715d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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