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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 250

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Rev Log message Author Age Path
246 Added some older files plus the first syn script creep 5612d 06h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
243 Fixing STA_IDY bug creep 5653d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
242 Bug regardind the STA_IDY opcode creep 5654d 03h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
212 Bug #56: ZPX page crossing. creep 5680d 07h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5683d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
202 Bug #49: RTI and RTS behavior was recoded. creep 5686d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
200 Bug #48: SP wrong after decrement. creep 5686d 03h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
199 Fixed two warning messages at the FSM. creep 5686d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
196 Syncing both repositories. creep 5686d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
195 FSM was locking on TSX/TXS. creep 5687d 03h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
194 Fixing bug #45 creep 5687d 06h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
146 Fixed ticket #13: reset behavior in the FSM. creep 5708d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5714d 05h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
120 Added some extra commentaries. creep 5716d 02h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
117 Fixed the top level and connected the entire project. creep 5716d 06h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
115 Renamed the signal control. It is mem_rw now. creep 5716d 07h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
112 Created a global timescale file for the project. creep 5716d 07h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
111 Performed some linting after coding was finished. creep 5716d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5717d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
109 PLA and PLP are coded and simulated. creep 5717d 02h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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