URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Rev 54

Rev	Log message	Author	Age	Path
52	Enabled own printf function using UART as output	julius	5668d 16h	/test_project/trunk/bench/sysc/src/OrpsocMain.cpp
51	Added SystemC Uart model	julius	5671d 06h	/test_project/trunk/bench/sysc/src/OrpsocMain.cpp
50	Tracing enabled on Verilator model	julius	5671d 20h	/test_project/trunk/bench/sysc/src/OrpsocMain.cpp
48	Closer to working verilator build	julius	5672d 21h	/test_project/trunk/bench/sysc/src/OrpsocMain.cpp
47	Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly	julius	5673d 00h	/test_project/trunk/bench/sysc/src/OrpsocMain.cpp
44	Beginnings of verilator build - much still to do but the design can now at least be verilated	julius	5681d 01h	/test_project/trunk/bench/sysc/src/OrpsocMain.cpp