URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] [or1200_monitor.v] - Rev 52

Rev	Log message	Author	Age	Path
52	Enabled own printf function using UART as output	julius	6016d 03h	/test_project/trunk/bench/verilog/or1200_monitor.v
39	Removed auto logging of processor state, added option to enable it in makefile, documented way the tests are done in makefile and that should probably be moved to some readme at some point	julius	6029d 12h	/test_project/trunk/bench/verilog/or1200_monitor.v
34	Fixed up couple of things. Changed way the test name is defined in sim Makefile	julius	6030d 14h	/test_project/trunk/bench/verilog/or1200_monitor.v
31	Further progress with orpsoc test setup	julius	6032d 07h	/test_project/trunk/bench/verilog/or1200_monitor.v
30	Updating bench	julius	6034d 12h	/test_project/trunk/bench/verilog/or1200_monitor.v