OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] [or1200_monitor.v] - Rev 57

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 Enabled own printf function using UART as output julius 5675d 00h /test_project/trunk/bench/verilog/or1200_monitor.v
39 Removed auto logging of processor state, added option to enable it in makefile, documented way the tests are done in makefile and that should probably be moved to some readme at some point julius 5688d 09h /test_project/trunk/bench/verilog/or1200_monitor.v
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5689d 11h /test_project/trunk/bench/verilog/or1200_monitor.v
31 Further progress with orpsoc test setup julius 5691d 04h /test_project/trunk/bench/verilog/or1200_monitor.v
30 Updating bench julius 5693d 09h /test_project/trunk/bench/verilog/or1200_monitor.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.