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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 34

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34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5633d 15h /test_project/trunk/bench/verilog/orpsoc_testbench.v
32 Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim julius 5635d 07h /test_project/trunk/bench/verilog/orpsoc_testbench.v
31 Further progress with orpsoc test setup julius 5635d 08h /test_project/trunk/bench/verilog/orpsoc_testbench.v
30 Updating bench julius 5637d 13h /test_project/trunk/bench/verilog/orpsoc_testbench.v
26 Adding testbench and makefile update julius 5638d 17h /test_project/trunk/bench/verilog/orpsoc_testbench.v

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