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Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 40

Rev	Log message	Author	Age	Path
40	Change name of file and module of orpsoc_top module	julius	5666d 00h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
34	Fixed up couple of things. Changed way the test name is defined in sim Makefile	julius	5667d 03h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
32	Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim	julius	5668d 19h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
31	Further progress with orpsoc test setup	julius	5668d 20h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
30	Updating bench	julius	5671d 01h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
26	Adding testbench and makefile update	julius	5672d 05h	/test_project/trunk/bench/verilog/orpsoc_testbench.v